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Electronics (ECE) - MCQ Practice Questions

Practice free Electronics (ECE) multiple-choice questions with detailed answers and explanations. Perfect for competitive exam preparation.

400 questions | 100% Free

Q.21Hard

The thermal runaway condition in a BJT occurs because:

Q.22Hard

The charge storage time in a BJT switch is primarily due to:

Q.23Hard

In a PIN diode used as an RF switch, the operating principle is based on:

Q.24Hard

The noise figure of an amplifier is defined as:

Q.25Hard

The substrate effect in a MOSFET causes:

Q.26Hard

The frequency response of a BJT amplifier is limited at high frequencies primarily by:

Q.27Hard

A tunnel diode exhibits negative differential resistance. At what operating point is the dynamic resistance most negative?

Q.28Hard

A CMOS logic gate has static power dissipation. Which phenomenon is primarily responsible for this in 2024 technology nodes?

Q.29Hard

A MESFET (Metal-Semiconductor FET) differs from a JFET primarily in which aspect?

Q.30Hard

In a heterostructure bipolar transistor (HBT), the wide bandgap material in the emitter provides which advantage?

Q.31Hard

For a 3-bit Johnson counter, the maximum count is:

Q.32Hard

Design a 3-bit Up/Down counter. If control signal C=1 for Up and C=0 for Down, which additional gates are required in a synchronous design?

Q.33Hard

In Hamming code for single error correction, if the total number of data bits is 16, how many parity bits are required?

Q.34Hard

A SRAM cell requires how many transistors for a 1-bit storage?

Q.35Hard

In pipelined architecture, what does increasing the number of pipeline stages primarily result in?

Q.36Hard

How does the Kogge-Stone adder compare to the Ripple Carry Adder in terms of propagation delay for a 32-bit addition?

Q.37Hard

In a complex digital system, what does 'Setup time' refer to?

Q.38Hard

A Moore FSM differs from a Mealy FSM in which aspect?

Q.39Hard

What is the maximum frequency operation for a circuit with total propagation delay of 50 ns?

Q.40Hard

In a pipelined architecture with 5 stages, what is the ideal speedup compared to non-pipelined execution?