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Electronics (ECE) - MCQ Practice Questions

Practice free Electronics (ECE) multiple-choice questions with detailed answers and explanations. Perfect for competitive exam preparation.

400 questions | 100% Free

Q.1Hard

For a 3-bit Johnson counter, the maximum count is:

Q.2Hard

Design a 3-bit Up/Down counter. If control signal C=1 for Up and C=0 for Down, which additional gates are required in a synchronous design?

Q.3Hard

In Hamming code for single error correction, if the total number of data bits is 16, how many parity bits are required?

Q.4Hard

A SRAM cell requires how many transistors for a 1-bit storage?

Q.5Hard

In pipelined architecture, what does increasing the number of pipeline stages primarily result in?

Q.6Hard

How does the Kogge-Stone adder compare to the Ripple Carry Adder in terms of propagation delay for a 32-bit addition?

Q.7Hard

In a complex digital system, what does 'Setup time' refer to?

Q.8Hard

A Moore FSM differs from a Mealy FSM in which aspect?

Q.9Hard

What is the maximum frequency operation for a circuit with total propagation delay of 50 ns?

Q.10Hard

In a pipelined architecture with 5 stages, what is the ideal speedup compared to non-pipelined execution?

Q.11Hard

A combinational logic circuit implements a function where output Y = (A'BC) + (AB'C) + (ABC'). After minimization using K-map, the circuit requires minimum number of gates. Which of the following is the simplified expression?