Electronics (ECE) - MCQ Practice Questions
Practice free Electronics (ECE) multiple-choice questions with detailed answers and explanations. Perfect for competitive exam preparation.
400 questions | 100% Free
For a 3-bit Johnson counter, the maximum count is:
Design a 3-bit Up/Down counter. If control signal C=1 for Up and C=0 for Down, which additional gates are required in a synchronous design?
In Hamming code for single error correction, if the total number of data bits is 16, how many parity bits are required?
A SRAM cell requires how many transistors for a 1-bit storage?
In pipelined architecture, what does increasing the number of pipeline stages primarily result in?
How does the Kogge-Stone adder compare to the Ripple Carry Adder in terms of propagation delay for a 32-bit addition?
In a complex digital system, what does 'Setup time' refer to?
A Moore FSM differs from a Mealy FSM in which aspect?
What is the maximum frequency operation for a circuit with total propagation delay of 50 ns?
In a pipelined architecture with 5 stages, what is the ideal speedup compared to non-pipelined execution?
A combinational logic circuit implements a function where output Y = (A'BC) + (AB'C) + (ABC'). After minimization using K-map, the circuit requires minimum number of gates. Which of the following is the simplified expression?