Electronics (ECE) - MCQ Practice Questions

In a 4-bit ripple counter using negative edge-triggered flip-flops, if the input frequency is 16 MHz, what is the frequency at the output of the third flip-flop?

Which logic gate produces HIGH output only when both inputs are different?

A SR flip-flop with S=0, R=0 results in:

The Gray code for decimal 5 is:

In a synchronous counter design, what is the main advantage over asynchronous counters?

A 3-to-8 decoder has how many output lines, and what is the number of active outputs for any single input combination?

In Booth's multiplication algorithm, which sequence of multiplier bits requires the fewest operations?

What is the setup time in a flip-flop?

For a modulo-6 counter using JK flip-flops, how many flip-flops are required at minimum?

Which multiplexer configuration is used to implement any Boolean function with minimum gates?

In VHDL, what does the 'rising_edge' function detect?

A 4-bit binary subtractor using 2's complement method requires:

In a magnitude comparator for 4-bit numbers, if A > B, A = B, and A < B outputs are provided, what is the total number of output combinations possible?

What is the hold time in a flip-flop, and why is it critical?

Which of the following is NOT a characteristic of ROM (Read-Only Memory)?

In a 16×4 RAM, what do the numbers 16 and 4 represent respectively?

Design a 3-bit Up/Down counter. If control signal C=1 for Up and C=0 for Down, which additional gates are required in a synchronous design?

In a cascaded 4-bit counter system where two 4-bit counters are connected, what maximum count value can be achieved?

Which encoding scheme minimizes errors during binary-to-decimal conversion in digital systems?

In a state machine with 7 states, how many flip-flops are needed for the state register?