Electronics (ECE) - MCQ Practice Questions

What is the main advantage of using CMOS technology over NMOS in digital circuits?

In a JK flip-flop, what happens when both J and K inputs are 1?

A multiplexer with 16 inputs requires how many select lines?

Which of the following is the correct Boolean expression for De Morgan's Law?

What is the propagation delay in a ripple counter compared to a synchronous counter?

In a 4:2 encoder, if input line 5 is active, what is the output?

What is the primary purpose of a Schmitt trigger in digital electronics?

In combinational logic design, what is the sum-of-products (SOP) form?

What does the term 'fanout' mean in digital logic circuits?

In a 3-bit binary counter, how many clock pulses are needed to complete one full cycle?

Which type of latch is transparent when the control signal is HIGH?

What is the output frequency of a 4-bit ripple counter when driven by a 16 MHz clock?

Which of the following statements about asynchronous reset is TRUE?

In a complex digital system, what does 'Setup time' refer to?

A Moore FSM differs from a Mealy FSM in which aspect?

What is the maximum frequency operation for a circuit with total propagation delay of 50 ns?

In a pipelined architecture with 5 stages, what is the ideal speedup compared to non-pipelined execution?

Which of the following is a non-volatile memory type commonly used in embedded systems?

In a 4-bit synchronous binary counter using JK flip-flops, if the clock frequency is 10 MHz, what is the maximum counting frequency at the MSB output?

A combinational logic circuit implements a function where output Y = (A'BC) + (AB'C) + (ABC'). After minimization using K-map, the circuit requires minimum number of gates. Which of the following is the simplified expression?