Electrical Engg (EEE) - MCQ Practice Questions

Which of the following is a characteristic of combinational circuits?

A full adder can be implemented using how many NAND gates minimum?

In the 2024-25 examination pattern, which logic family provides the lowest power consumption?

A 3-to-8 decoder with active-low outputs has how many output lines at logic 0 when the input is 101?

In a Priority encoder, when multiple inputs are high simultaneously, which input gets priority?

The setup time of a flip-flop is defined as:

In a Karnaugh map, what does a larger group of adjacent 1's represent?

A synchronous BCD counter counts from 0000 to 1001, then resets to 0000. This requires modification of a standard 4-bit counter using:

Which Boolean algebra theorem states that A + A·B = A?

In a multiplexer, the number of select lines required to select from 16 data inputs is:

The propagation delay in a synchronous counter is:

Which of the following is used to convert analog signals to digital for processing?

In Quine-McCluskey method, prime implicants are:

A JK flip-flop with J=1, K=1 and clock pulse will:

The hold time specification for a flip-flop ensures that:

In a 8-bit parallel-in serial-out (PISO) shift register, how many clock pulses are needed to output all data?

Which characteristic distinguishes CMOS gates from TTL gates in practical applications?

In a Gray code counter, consecutive counts differ by exactly:

In a 4-to-1 multiplexer, how many select lines are required?

What is the output of an SR flip-flop when S=1 and R=1 (NOR gate implementation)?