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Electrical Engg (EEE) - MCQ Practice Questions

Practice free Electrical Engg (EEE) multiple-choice questions with detailed answers and explanations. Perfect for competitive exam preparation.

670 questions | 100% Free

Q.41Easy

Which Boolean theorem states that A + 0 = A and A · 1 = A?

Q.42Easy

In a ripple counter with 4 flip-flops, what is the maximum count?

Q.43Easy

What is the primary advantage of CMOS logic over TTL logic in modern designs?

Q.44Medium

In a D flip-flop, the output Q follows the input D on the occurrence of which signal?

Q.45Medium

Which type of ADC provides the fastest conversion?

Q.46Medium

What is the output frequency of a decade counter (MOD-10 counter) when input frequency is 1 MHz?

Q.47Easy

In a multiplexer with 8 input lines, how many output lines are present?

Q.48Medium

The setup time of a flip-flop is defined as the minimum time during which the input must be stable:

Q.49Medium

Which of the following logic families has the highest power dissipation?

Q.50Easy

De Morgan's theorem states that (A·B)' equals:

Q.51Medium

A 16:1 multiplexer requires how many select lines to uniquely identify each input?

Q.52Medium

In asynchronous (ripple) counters, the propagation delay issue leads to:

Q.53Medium

Which digital circuit is used to convert parallel data into serial form?

Q.54Medium

The Boolean expression A·B + A·B' can be simplified to:

Q.55Hard

In a synchronous counter design, all flip-flops receive the clock signal simultaneously. This arrangement primarily eliminates:

Q.56Hard

A Schmitt trigger input is used in digital circuits primarily to:

Q.57Hard

When implementing a 3-variable Boolean function using a 2-to-1 multiplexer instead of a 8-to-1, one variable must be:

Q.58Easy

A 4-bit binary counter requires how many flip-flops to count from 0 to 15?

Q.59Easy

Which logic gate produces a HIGH output only when all inputs are HIGH?

Q.60Easy

What is the minimum number of NAND gates required to implement a NOT gate?