Electrical Engg (EEE) - MCQ Practice Questions

In a J-K flip-flop, when J=1 and K=1, the output will:

What is the hold time of a flip-flop?

A 32:1 multiplexer can be constructed using how many 4:1 multiplexers?

Which of the following flip-flops is most suitable for frequency division applications?

In 2's complement representation, what is the range of numbers for an 8-bit system?

Which characteristic of CMOS logic makes it suitable for portable devices?

How many address lines are required for a 4GB memory system?

In a priority encoder, what determines which input is encoded when multiple inputs are active?

What is the main advantage of Gray code over binary code in digital systems?

A 3-to-8 decoder has how many output lines?

What is the hold time constraint violation in sequential circuits?

Which digital logic family provides the best balance between speed and power consumption?

In a 4-bit BCD adder, what is the maximum sum that can be represented without requiring correction?

What is the primary function of a state machine in digital design?

In a 8-bit barrel shifter, how many control bits are required to specify any shift amount?

In a synchronous counter design, what is the primary advantage over asynchronous counters?

Which of the following is the correct relationship for setup time in sequential circuits?

A Karnaugh map with 5 variables requires a minimum of how many cells?

In a multiplexer circuit, if there are 16 output lines, how many select lines are required?

Which logic family has the highest noise margin among the following?