Electrical Engg (EEE) - MCQ Practice Questions

In a BCD (Binary Coded Decimal) counter, what is the maximum count value?

Which of the following represents the De Morgan's law correctly?

In an SR flip-flop, what happens when both S and R inputs are 1 simultaneously?

A Johnson counter (twisted ring counter) with n flip-flops produces how many unique states before repeating?

In FPGA design, what does LUT (Lookup Table) primarily function as?

What is the Fan-out limit of a TTL gate, and what does it signify?

Which semiconductor technology provides the lowest static power consumption?

In a sequential logic circuit, metastability occurs when the input changes relative to the clock edge. How can this be minimized?

What is the characteristic equation of a D flip-flop?

In asynchronous sequential circuits, what is the primary concern regarding state transitions?

Which of the following correctly describes the difference between combinational and sequential logic?

In the context of digital signal processing, what is the Nyquist sampling theorem's requirement?

What is the main purpose of tristate logic (three-state logic) in digital circuits?

In a 4-bit binary counter using JK flip-flops, if the propagation delay of each flip-flop is 10 ns, what is the maximum counting frequency?

A combinational circuit has 6 input variables. The minimum number of rows required in its truth table is:

In a synchronous counter design using SR flip-flops with Karnaugh map minimization, which hazard is most critical in the implementation?

A 3-to-8 decoder is used in a digital system. How many AND gates with minimum inputs are required?

In a Mealy state machine design for a sequence detector (detecting '101'), the output depends on:

What is the setup time requirement for a D flip-flop in a shift register operating at 100 MHz clock frequency?

A priority encoder with 8 inputs has the highest priority assigned to the MSB. If inputs I7=1, I5=1, I3=1, and all others are 0, what is the output?